1. Field of the Invention
The present invention relates to a method and a display apparatus, and more particularly to a driving method and a liquid crystal display apparatus.
2. Description of the Art
A liquid crystal display device displays images by controlling light transmittance of a liquid crystal material using an electric field. The liquid crystal display device comprises a liquid crystal display panel having a pixel matrix and a drive circuit for driving the liquid crystal display panel.
FIG. 1 is a block schematic diagram of a liquid crystal display device according to the related art. In FIG. 1, a liquid crystal display is connected to a system driver 1 installed in a computer system, and includes a graphic card 2 for supplying video data adapted to a liquid crystal display 3. The graphic card 2 converts the video data and supplies the converted video data to the liquid crystal display 3, wherein the video data includes red (R), green (G), and blue (B) video data. In addition, the graphic card 2 generates control signals that include a clock signal (DCLK) and horizontal and vertical synchronization signals (Hsync, Vsync) suitable for the resolution of the liquid crystal display 3.
The liquid crystal display 3 includes a liquid crystal display panel 10, a data driver 6 for driving data lines (D1 to Dm) of the liquid crystal display panel 10, a gate driver 8 for driving gate lines (G1 to Gn) of the liquid crystal display panel 10, a timing controller 4 for controlling a drive timing of the data and the gate drivers 6 and 8, a power supply circuit 14 generating a driving voltage necessary to drive the liquid crystal display 3, and a gamma circuit 12 supplying a gamma voltage to the data driver 6.
The power supply circuit 14 generates driving voltages necessary for driving the liquid crystal display 3 (i.e., gate high voltage, gate low voltage, gamma reference voltage, and common voltage) using the voltage received from a system power supply (not shown) of the system driver 1. Accordingly, the power supply circuit 14 supplies the driving voltages to the timing controller 4, the data driver 6, the gate driver 8, and the gamma circuit 12.
The liquid crystal display panel 10 is connected to a thin film transistor (TFT) formed at each intersection of an n-number of the gate lines (G1 to Gn) and an m-number of the data lines (D1 to Dm) and includes liquid crystal cells connected to the respective thin film transistor and arranged in a matrix pattern. The thin film transistor supplies video data from the data lines (D1 to Dm) to the liquid crystal cell in response to gate signals from the gate lines (G1 to Gn). Since the liquid crystal cell comprises a pixel electrode connected to a common electrode and a thin film transistor facing each other in which a liquid crystal is located thereto, the liquid crystal display is equivalently expressed as a liquid crystal capacitor (Clc). The liquid crystal cell includes a storage capacitor (Cst) connected to a pre-staged gate line in order to maintain the data voltage charged to the liquid crystal capacitor (Clc) until the next data voltage is received.
The gate driver 8 sequentially supplies the gate high voltage signal to the gate lines (G1 to Gn) according to a gate start pulse signal (GSP) received from the timing controller 4. Accordingly, the gate driver 8 includes a plurality of gate drive integrated circuits (not shown), commonly referred to as gate driving ICs, for separately and sequentially driving the gate lines (G1 to Gn). Each of the gate driving ICs include a shift register responding to the gate start pulse signal (GSP) and a gate shift clock signal (GSC) provided from the timing controller 4. In addition, the gate driving ICs sequentially generate a gate high voltage signal and include a level shifter for shifting voltages of the gate high voltage signal to suitable levels for driving the thin film transistor. When the gate start pulse signal (GSP) is supplied from the timing controller 4, the gate driving ICs respond to the gate shift clock signal (GSC) and sequentially supplies the gate high voltage signal having one horizontal period (1H) to the gate lines (G1 to Gn) by performing a shift operation.
The data driver 6 converts the R, G, and B data signals from the timing controller 4 into analog signals and supplies the video data of one horizontal line for each horizontal period in which the gate high voltage signal is supplied to the gate line (G1 to Gn) to the data lines (DL1 to DLm). Accordingly, the data driver 6 includes a shift register part supplying sequential sampling signals, a latch part providing signals at the same time as sequentially latching the video data in response to the sampling signal, a digital-analog converter part converting the digital video data from latch part into analog video data, and an output buffer part providing signals as buffering the analog video data from the digital-analog converter part. Positive and negative gamma voltages are set in order to have voltage levels different from each other according to the voltage level of the video data from gamma circuit 12 in a digital-analog converter part of the data driver 6. As the positive and the negative gamma voltages are supplied to the video data, the video data adapts gamma characteristics that are selected by a polarity inversion signal (POL) from the timing controller 4 and is supplied to the data lines (D1 to Dm) in response to a source output enable signal (SOE).
In order to drive the liquid crystal display panel 10, the timing controller 4 responds to a clock signal and horizontal and vertical synchronization signals (Hsync, Vsync) from the graphic card 2, and controls driving timing of the gate driver 8 and the data driver 6. For example, the timing controller 4 responds to the clock signal and the horizontal and the vertical synchronization signals (Hsync, Vsync), generates a gate clock signal, a gate control signal, and a gate start pulse, and supplies the signals to the gate driver 8. In addition, the timing controller 4 responds to an input clock signal and horizontal and vertical synchronization signals (Hsync, Vsync), and generates a data enable signal and supplies the signals to the data driver 6. Moreover, the timing controller 4 supplies the R, G, and B video data from the graphic card 2 to the data driver 6 in synchronization with the polarity inversion signal and the data enable signal.
During driving of the liquid crystal panel 10, since the thin film transistor (TFT) is turned ON by the gate high voltage (Vgh) supplied to the gate line (G), video voltage signals supplied to the data lines (DL1 to DLm) are charged to the liquid crystal capacitor (Clc). Subsequently, since the thin film transistor is turned OFF by the gate low voltage (Vgl) supplied to the gate line (G), the video voltage charged to the liquid crystal capacitor (Clc) is maintained until the next data voltage is supplied. Accordingly, when the gate high voltage (Vgh) and the gate low voltage (Vgl) are supplied to a pre-staged gate line (Gn-1), the storage capacitor (Cst) connected in parallel to the liquid crystal capacitor (Clc) is charged and maintains the charged voltage higher than voltage charged to the liquid crystal capacitor during a turned OFF period. Thus, fluctuations of the voltages charged to the liquid crystal capacitor (Clc) can be minimized.
In order to drive the liquid crystal cells of the liquid crystal display panel, various inversion driving methods, such as frame inversion, line-column inversion, and dot inversion, are commonly used in the liquid crystal display device. During the frame inversion driving method, the polarity of the data signal supplied to the liquid crystal cells of the liquid crystal display panel is inverted whenever a frame is changed. During the line-column inversion method, the polarity of the data signal supplied to the liquid crystal cells is inverted according to the line (column) of the liquid crystal display panel. During the dot inversion method, a data signal is supplied to each liquid crystal cell of the liquid crystal display panel, wherein the data signal has a polarity contrary to the data signal supplied to adjacent liquid crystal cells along vertical and horizontal directions. In addition, during the dot inversion method, the polarity of the data signals supplied to all the liquid crystal cells of the liquid crystal display panel are inverted for each frame. Among the various inversion driving methods, the dot inversion method provides excellent picture quality, as compared to the frame and line-column inversion methods. Driving of the frame and line-column inversion methods is carried out as the data driver 6 responds to the polarity inversion signal supplied to the data driver 6 from the timing controller 4.
In general, liquid crystal display devices are commonly driven at a frame frequency of 60 Hz. However, in devices, such as a notebook computer, requiring low power consumption, the frame frequency is lowered to 50˜30 Hz, thereby creating a flicker phenomenon during the dot inversion method. Accordingly, a 2-dot inversion method is used to drive the liquid crystal display panel.
FIGS. 2A and 2B are diagrams showing 2-dot inversion polarity patterns applied to the liquid crystal display panel of FIG. 1 according to the related art. In FIGS. 2A and 2B, the polarities of data signals are supplied to liquid crystal cells of the liquid crystal display panel using a two-dot inversion method having odd- and even-numbered frames. In the odd- and even-numbered frames, the polarity of the data signal is inverted by the liquid crystal cell similar to the dot inversion system along a horizontal direction, but is inverted by the 2-dots along a vertical direction.
FIGS. 3A and 3B are diagrams showing additional 2-dot inversion polarity patterns applied to the liquid crystal display panel of FIG. 1 according to the related art. In FIGS. 3A and 3B, the polarities of data signals are supplied to liquid crystal cells of the liquid crystal display panel using a 2-dot inversion method including odd-and even-numbered frames. In the odd- and even-numbered frames, the polarity of the data signal is inverted by the liquid crystal cell similar to the dot inversion system along a horizontal direction, but is inverted by 2-dots along a vertical direction except for a first horizontal line.
FIG. 4 is a waveform diagram of polarity inversion signals applied to a data driver of the liquid crystal display panel of FIG. 1 according to the related art. In order to drive the liquid crystal display using the 2-dot inversion method, the timing controller 4 generates the polarity inversion signal (POL) for the liquid crystal cell driven by the 2-dot inversion method using the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) received from the graphic card 2. In addition, the timing controller 4 generates the data enable signal (DE) for supplying the data signal to the liquid crystal cell using of the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) received from the graphic card 2. The data enable signal (DE) generated by the timing controller 4 is divided into a back porch period, which spans from the last point of time of the vertical synchronization signal (Vsync) to the starting point of time of the data enable signal (DE), and an effective data period when effective data is supplied during one vertical synchronization period. Accordingly, the back porch period is a period between a rising edge of the data signal at the first data line, after the vertical synchronization signal (Vsync) is over, among a blanking period in which effective data does not exist in one frame driven by the one vertical synchronization signal (Vsync). Furthermore, the polarity of the polarity inversion signal (POL) generated by the timing controller 4 is inverted by the two horizontal synchronization signals (Hsync) during the period of the vertical synchronization signal (Vsync).
FIG. 5 is a circuit diagram of a polarity inversion signal generator for generating the polarity inversion signals of FIG. 4 according to the related art. In FIG. 5, the timing controller 4 includes a polarity inversion signal generator 30 having a first D flip-flop (DF1) supplying a first frequency division to the horizontal synchronization signal (Hsync), a second D flip-flop (DF2) supplying a second frequency division to an output from an inverted output terminal (BQ1) of the first D flip-flop (DF1), a reset circuit 32 for resetting frames of logic states of the first and the second D flip-flop (DF1, DF2), and a multiplexer for selecting an input signal supplied from a non-inversion output terminal (Q2) and an inverted output terminal (BQ2) of the second D flip-flop (DF2) to supply the selected input signal to the data driver.
In FIG. 5, the first D flip-flop (DF1) receives the inverted horizontal synchronization signal (Hsync) as a clock signal to supply the first frequency division to the received signal to provide the frequency-divided signal. The second D flip-flop (DF2) supplies the second frequency division to the input signal from the first D flip-flop (DF1) to provide the frequency-divided signal. For example, the second D flip-flop (DF2) supplies frequency-division twice to the horizontal synchronization signal (Hsync).
FIG. 6 is a waveform diagram of polarity inversion signals applied to a data driver according to the related art. In FIG. 6, the first D flip-flop (DF1) synchronizes a signal, which is fed-back from its own inversion output terminal (BQ1) and is received at an input terminal (D), with the rising edge of the inverted horizontal synchronization signal (Hsync) to generate a first polarity inversion signal (POL1), thereby supplying the generated first polarity inversion signal (POL1) to the clock input terminal of the second D flip-flop (DF2) through the inversion output terminal (BQ1). Accordingly, the first polarity inversion signal (POL1) is inverted in polarity for each falling edge of the horizontal synchronization signal (Hsync).
In FIG. 6, the second D flip-flop (DF2) synchronizes a signal, which is fed-back from its own inversion output terminal (BQ2) and is received at an input terminal (D), with the rising edge of the first polarity inversion signal (POL1) from the inversion output terminal (BQ1) of the first D flip-flop (DF1) to generate a second polarity inversion signal (POL2). Accordingly, the second polarity inversion signal (POL2) is inverted in polarity for each second period of the horizontal synchronization signal (Hsync). In addition, the second polarity inversion signal (POL2) generated at the second D flip-flop (DF2) is supplied to a first input terminal of the multiplexer (MUX) through the non-inversion output terminal (Q2) and is supplied to a second input terminal of the multiplexer (MUS) through the inversion output terminal (BQ2).
In FIG. 5, the reset circuit 32 includes a fourth D flip-flop (DF4) delaying the vertical synchronization signal (Vsync) received in response to the clock signal (CLK) by one clock period, a fifth D flip-flop (DF5) delaying the input signal from non-inversion output terminal of the fourth D flip-flop (DF4) by one clock period in response to the clock signal (CLK), an XOR gate 34 for Exclusive-OR-Logic operation between the input signal from non-inversion output terminal (Q5) of the fifth D flip-flop (DF5) and the vertical synchronization signal (Vsync), and a NAND gate for NAND-Logic operation between the output signal (Q6) from XOR gate 34 and the vertical synchronization signal (Vsync). The reset circuit 32 generates the reference to the horizontal synchronization signal (Hsync) in order to invert the vertical synchronization signal (Vsync) for each frame. In addition, the polarity inversion signal (POL2) of 2 dot inversion system is generated by the first and the second D flip-flops (DF1, DF2) including a reset signal (VSRB) for resetting the logic states of the first and the second D flip-flops (DF1, DF2) for each frame on the basis of the vertical synchronization signal (Vsync).
The multiplexer MUX selects input signals provided to each of the first and the second input terminals from the inverted output terminal (BQ2) and the non-inverted output terminal (Q2) of the second D flip-flop (DF2), and supplies the selected signal to the data driver 6 (in FIG. 1). Accordingly, the reset circuit 30 includes a third D flip-flop (DF3) that generates a selection signal (CS) inverted for each frame unit and is connected to a selection signal input terminal of the multiplexer MUX. The third D flip-flop (DF3) receives a feedback signal from its own inverted output terminal (BQ3) synchronized at a rising edge of the inverted vertical synchronization signal (Vsync), and generates and supplies the selection signal (CS) to the selection signal input terminal of the multiplexer MUX through a non-inverted output terminal (Q3). Since the selection signal is generated on the basis of the vertical synchronization signal (Vsync), the selection signal (CS) is inverted for each frame. Accordingly, the multiplexer MUX performs an inversion in response to the second polarity inversion signal (POL2) for each selection signal (CS) from the third D flip-flop (DF3) and supplies the inverted signal to the data driver 6.
FIG. 7 is a schematic circuit diagram of a MUX part of a data driver according to the related art. In FIG. 7, the data driver 6 (in FIG. 1) supplies the polarity of the video data to the liquid crystal display panel 10 (in FIG. 1) using the 2-dot inversion method according to the polarity inversion signal (POL2) received from the timing controller 4 (in FIG. 1) using a plurality of multiplexers 52. Accordingly, each of the multiplexers 52 of the data driver 6 (in FIG. 1) includes first and second input terminals to which positive (+) and negative (−) data voltages are supplied from a digital-analog converter (not shown), a selection signal input terminal to which the polarity inversion signal (POL2) received from the timing controller 4 (in FIG. 1) is supplied, and an output terminal connected to the data lines (DL1 to DLm) through a buffer (not shown). In FIG. 7, an inverter 54 is connected to the selection signal input terminal of even-numbered ones of the multiplexers 52 for inverting the polarity inversion signal (POL2) received from the timing controller 4 (in FIG. 1).
Accordingly, the polarity of the video data supplied to the liquid crystal display panel 10 from the data driver 6 (in FIG. 1), as shown in FIGS. 2A, 2B, 3A, and 3B, are converted to have the polarity using the 2-dot inversion method since a start point of time of the polarity inversion signal (POL2) differs according to the number of the horizontal synchronization signal (Hsync) received during the back porch period of the data enable signal (DE).
When the number of the horizontal synchronization signal (Hsync) received to the back porch period of the data enable signal (DE) is even numbered, the polarity of the effective video data of the data enable signal (DE) is supplied to the liquid crystal display panel 10 using the 2-dot inversion method, as shown in FIGS. 2A and 2B, according to the second polarity inversion signal (POL2) beginning from a point “A” of time of the second polarity inversion signal (POL2), as shown in FIG. 6. Furthermore, when the number of the horizontal synchronization signal (Hsync) received to the back porch period of the data enable signal (DE) is odd numbered, the polarity of the effective video data of the data enable signal (DE) is supplied to the liquid crystal display panel 10 using the 2-dot inversion method, as shown in FIGS. 3A and 3B, according to the second polarity inversion signal (POL2) beginning from a point “B” of time of the second polarity inversion signal (POL2), as shown in FIG. 6.
FIGS. 8A and 8B are diagrams showing flicker inspection patterns of a 2-dot inversion system according to the related art. In FIG. 8A, during the 2-dot inversion driving method, a flicker inspection pattern (i.e., the first flicker inspection pattern) shows that the polarity of data supplied to the liquid crystal display panel is changed by a 1-dot unit along a horizontal direction and is changed by a 2-dot unit along a vertical direction and is supplied as a half-gray pattern to a green sub-pixel of the negative polarity (−), and a black pattern to red and blue sub-pixels. Accordingly, if the first flicker inspection pattern is displayed on the liquid crystal display panel driven using the 2-dot inversion method, the flicker can be adjusted since components of a ½-frame frequency, i.e., frame frequency divided in half, appear due to the half-gray pattern of the negative polarity (−).
In FIG. 8B, during the 2-dot inversion driving method, the flicker inspection pattern (i.e., the second flicker inspection pattern) shows that the polarity of data supplied to the liquid crystal display panel is changed by a 1-dot unit along a horizontal direction and is changed by a 2-dot unit along a vertical direction except for a first horizontal direction that supplies a half-gray pattern to a green sub-pixel of the negative polarity (−), and a black pattern to red and blue sub pixels. Accordingly, if the second flicker inspection pattern is displayed on the liquid crystal display panel driven using the 2-dot inversion method, the flicker can be adjusted since components of a ½-frame frequency, i.e., frame frequency divided in half, appear due to the half-gray pattern of the negative polarity (−).
FIGS. 9A and 9B are diagrams showing flicker inspection patterns according to the related art. In FIG. 9A, inspection of a flicker adjustment for the liquid crystal display using the 2-dot inversion driving method includes adjusting the flicker by a first flicker inspection pattern (a) using the 2-dot inversion method (b), wherein the data polarity is changed by the 1-dot unit along the horizontal direction and is changed by the 2-dot unit along the vertical direction except for the first horizontal direction. Accordingly, a flicker inspection pattern (c) is produced, wherein the positive polarity (+) and the negative polarity (−) are offset from each other. Thus, flicker cannot be seen on the liquid crystal display panel due to the frame frequency component, and the flicker cannot be adjusted.
In FIG. 9B, inspection of a flicker adjustment for the liquid crystal display using the 2-dot inversion driving method includes adjusting the flicker by a first flicker inspection pattern (a) using the 2-dot inversion method (b), wherein the data polarity is changed by the 1-dot unit along the horizontal direction and is changed by the 2-dot unit along the vertical direction except for the first horizontal direction. Accordingly, a flicker inspection pattern (c) is produced, wherein the positive polarity (+) and the negative polarity (−) are offset from each other. Thus, flicker cannot be seen on the liquid crystal display panel due to the frame frequency component, and the flicker cannot be adjusted.
Accordingly, with respect to the driving method of the liquid crystal display using the 2-dot inversion driving method, since the polarity inversion signal (POL2) supplied to the data driver 6 becomes different according to the number of the horizontal synchronization signal received to the back porch period of the data enable signal (DE), the data polarity of the 2-dot inversion method supplied to the liquid crystal display panel 10 becomes different.